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Last Updated by Mark Lee on 06/03/97
The operating system has minimal requirements, and thus is kept as simple as possible. The main tasks that the operating system may perform may be divided into ?three? categories: 1) bootstrap code 2) interrupt handler code 3) context switching.
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The Bootstrap Code is the first set of instructions that the PC603 executes
upon coming out of /HRESET. This code writes to 603 internal configuration
registers to set up the proper running conditions, such as little-endian
operation, power-saving mode, enabling of caching and of address translation.
Also, this code may run power-on diagnostic tests, and initialize structures
(e.g. ramlogging, address translation)
Hardware Notes for PowerPC603 startup.
1) Upon power-up, the 603 vectors to the physical address
0XFFF0_0100
This is hardwired into the 603 and cannot be set. [1].6-18
Within the State Machine, this address is aliased to the page 0 SRAM. (Note
that since the upper order addresses are asserted, the page selects are
active for different parts of the board. During board modes other than
NORMAL mode, the aliasing is possible since the busctlr will only perform
reads from the page0 SRAM outside of normal mode. While in NORMAL mode, any
address which asserts the (page0_SRAM & (Bos_ORCA # Bos_SRAM # Bos_LUT) &
(Jon_ORCA # Jon_SRAM # Jon_LUT))
will be aliased to the exception table.
For a summary of which types of accesses are allowed in certain modes,
refer to the hardware page.
3) The instructions at 0xFFF0_0100 will serve to change to Little Endian code
then jump to the rest of the Boot_Code, located at 0x00103000. Note that
this address is a branch to get into the address range 0x00100000 -
0x001FFFFF. Thus, the PC of the 603 will be directly accessing the
page0SRAM, and avoids problems when it goes into NORMAL board mode.
The following is a software description of power-on sequences for the 603.
1) Boot_Code description:
VBOOT.S - Change to little endian mode, and branch to Boot_Code.
Enable Dynamic Power Management.
Initialize BAT registers.
Zero Time Base.
jump to main
MAIN.C - run init_regtest()
run init_memtest()
initialize proc structures for multi-tasking?
intialize ramlog
start monitor
MONITOR.C - sit and spin until interrupted by i960
4) At the end of an exception handler or the boot code, the RFI instruction
should be used to vector to a new instruction. RFI uses the value in the
SRR0 register as the return address.
This is the code that the 603 executes upon receiving interrupts.
*****List important interrupt handlers.
) The code in 0100 in the page 0 SRAM is the exception table. This address in
particular has been allocated to handle power-on and HRESET cases.
(For more details on exception handling, see [1] section 6).
) Handler for Interrupt from i960
o THe i960 will interrupt the 603 via the /SMI signal to start a new 603
application. Probably, the i960 will put a value in the GPREG which will
signify which process slot to start executing.
o When the 603 receives the interrupt, then it will vector to the SMI
interrupt handler in the table (address 0xFFF0_1400). This interrupt
handler will have to perform the following steps:
- change IBAT registers such that it maps the effective address (EA) of
the application code (whose range starts with address 0) to the right
physical address (assserting the Page0 bit, and remapping the EA to
the correct process slot).
- change stack frame pointer?
- issue RFI command to jump to the correct process slot and change back
to user-level code.
)Handler for interrupt from ORCA FPGAs:
o Poll interrupt store address on register interface
o Depending on the calue the interrupt handler will probably update a global
flag which will let some program loop in one of the application slots
end.
e.g.
start app code
loop until GLOBAL_FLAG set
process stream data from proper SRAM
assert interrupt acknowledge back to proper FPGA.
if GLOBAL_FLAG is set
for other FPGA process it
Interrupt back to i960 signalling completion of stream
process.
The 603 will vector to an offset from address 0x000n_nnnn where n_nnnn refers
to an offset described in Table 6-2, [1].6-3
Note that during NORMAL mode, the exception table address 0XFFF0_0100 is
aliased to the page 0 SRAM, as described above in note 1)
NOTE: during setup, the MSR[IP] should be cleared to ensure the correct address
for the exception table.
Context switching is performed to bring the 603 out of a monitor loop and to have it branch to an application code slot. See descripton below. Necessary steps: o Extract Parameter structure at stack structure to determine size and number parameters. o Take parameters out of parameter structure located at the bottom of the address space of the process slot and place them into GPreg's. Stack??!! - Should we save values of GPregs first? o program BAT registers to translate addr 0 to page 0 o change permision to user level o RFI to app code Parameter Passing ----------------------------------- Parameter Passing will comply with the model described elsewhere. It was designed to allow different size parameters to be passed. unsigned Integer (1-16 bytes) signed integer (1-16 bytes) floating point boolean false boolean true shared memory ID - id for accessing large of persistent data objects tagged shared memory ID - id for accessing large or persistent data objects which are aggregates of dissimilar data objects. Notes on 603 implementation of Parameter Passing: ================================================= The gcc compiler implemented for State Machine applications expects application parameters to be found in the 603 internal General Purpose Registers, starting with GPreg3.
PREILIMINARY MAKEFILE: A preliminary cross-compiler has been constructed to run on the RS6000's (miles.media.mit.edu or monk.media.mit.edu). SPECIAL NOTE ON OS MAKEFILE AND ENDIANNESS: Since the 603 is native big-endian, the first instructions that it sees upon power-up/hard reset must be in big endian. (The State machine itself is little endian since the rest of Cheops is little-endian.) This means that the first command in the exception table offset 0x00100 should write to the MSR register to set bit 31 to 1. (See [1].pg. 2-23 for MSR bit settings.) These commands which change the endianness must therefore be in big-endian themselves. To edit the object file to change the endianness manually, from emacs, open the file, then: 'M-x hexl-mode' - This will display the binary file in HEX with line numbers 'M-Ctrl-x' - Use this command to replace a HEX number 'Ctrl-x-s' - Save the fileImportant note on writing code to the Page 0 SRAM!!!!
The utilities that retrieve the coff file from disk will strip the program of all unnecessary coff info. to reduce its size. The text, data, and bss sections will be appended to produce one contiguous program block. In firmware (specifically the Pg0mar EPLD), any access to the PAGE 0 SRAM from the i960 will FLIP THE THIRD LOWEST ORDER ADDRESS BIT. This was done to facilitate word-swapping any data. This makes effective addressing in both the 603 and the i960 consistent. i.e. if i960 accesses consecutive addresses, say 0 through 64, then it will access the same data as the 603 would WHEN THE 603 IS IN LITTLE ENDIAN MODE.
The PowerPC 603's version of Little Endian bears further explanation. Upon power-up, the 603 is in big-endian mode. Changing the endianness (See [1], pg.2-43 for the code segment to do this.) means changing the byte order as if the 603 were running in 64-bit mode. Since we are running in 32-bit mode, this leads to a peculiar addressing scheme: Instruction fetch: The 603 recognizes that single beat fetches of instructions occur in word lengths. Thus, the bytes of the instruction are not reordered. However, every other instruction should be swapped. That is, given the following instruction code: 0x00100 ABCD 0x00104 EFGH 0x00108 IJKL 0x0010c MNOP where the letters A,B,...,P are used to specify bytes, the intruction fetch unit would access in the order: 0x00104 EFGH 0x00100 ABCD 0x0010c MNOP 0x00108 IJKL This is equivalent to the third lowest order address bit being negated. This seems to be the only difference in the instruction fetch. NOTE that the bytes within the instruction word should not be reordered. Data fetch: BYTE SIZED ACCESSES: ----------------------- When operating in Little-Endian mode, the 603 will reverse the address bits for data accesses. That is, if the following code is executed: lis r4, 0x0010 ori r4, r4, 0x2000 li r5, 0x005a stb r5, 0(r4) Then the address 0x00102007 will be put out on the bus. (As this is currently running without any address translation, it is unclear at what point the address is affected.) The general rule that the 603 seems to follow to calculate the new address is to change only the three lowest order address bits: 0b000 => 0b111 0b001 => 0b110 0b010 => 0b101 0b011 => 0b100 0b100 => 0b011 0b101 => 0b010 0b110 => 0b001 0b111 => 0b000 SHORT (16-bit) SIZED ACCESSES: ----------------------- The i960 orders shorts in the following way (little endian): Given the byte data: data: A B C D E F G H addr: 0 1 2 3 4 5 6 7 Shorts are interpreted: data: BA DC FE HG addr: 0 2 4 6 To get the PPC603 to read shorts the same way, 0b000 => 0b110 0b010 => 0b100 0b100 => 0b010 0b110 => 0b000
[1] PowerPC603 RISC Microprocessor User's Manual
IBM #MPR603UMU-01
1994
[2] Managing Projects with make
Andrew Oram and Steve Talbott
O'Reilly & Associates, Inc.
[3] Understanding and Using COFF
Gintaras R. Gircys
O'Reilly & Associates, Inc.
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