State Machine Stream Processor

State Machine Architecture

THIS PAGE CURRENTLY BEING UPDATED BY KEN KUNG AND MARK LEE!!

Last revised: 06/20/97

Table of Contents

Recent Developments

State machine will be undergoing the following phases (not necessarily in this order):

Background

The P2 processor board for Cheops is able to achieve real-time image processing rates by delegating computationally intensive tasks to specialized stream processors. However, Cheops incurs a substantial performance degradation when executing operations for which no special purpose processor exists.

State Machine Introduction

The State Machine subsystem works as a co-processing system to the host system. Like the many plug-in cards of a personal computer, it connects to the main bus of the host system. It is intended to help the host system to expedite some of its most demanding jobs. Its minimum functional requirement thus is to support the specific bus interface protocol of the host system. In our case, the State Machine card supports the bus interface protocol of the Cheops Imaging system.

The cheops bus interface protocol consists of a register interface (for control) and a stream interface (for DMA, which, in turn, consists of handshaking signals and data bus).

The rest of the subsystem deals with whatever functions the designer deems useful. We chose to put a GPP and certain amout of reconfigurable logic and memory subsystems.

State Machine Detailed Information

Publications


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