Proceedings of 2016 Symposia on VLSI Technology and Circuits, pp. C132-C133, 2015.
We envision single-level storage systems that can logically host and map numerous IoT devices on a single vast address space, where user programs can access those devices without having to be aware of the actual storage types or physical device locations. We introduce three pieces of caching technology for such IoT-oriented storage systems as small but concrete steps towards the aforementioned envisioned goal.
Using NAND flash memory suitable for typically small and mobile IoT devices, proof-of-concept, partial prototypes of a single-level storage system are implemented, where data can be accessed in a unified way regardless of whether it is on the DRAM or on the flash memory.
The following figure shows the proposed storage system allowing for load/store access to the flash memory with the aid of a storage memory management unit (SMMU), making the flash memory appear as huge main memory, along with the prototype board corresponding to the dotted rectangle part.
This may appear similar to virtual memory and memory-mapped IO, but our goal here is to use flash memory as main memory, and the main challenge is to hide limitations of flash memory such as a limited number of write cycles. The SMMU tries not to write cached DRAM data back to the flash memory and compresses it when write-back is necessary, eliminating 82% of write-back traffic for video playback as shown below.
Even with the use of DRAM cache and SMMU in the host, it is still desirable to have faster flash memory. The access latency of solid-state storage devices comes in part from the need to first read address translation information stored in the flash translation layer (FTL) in the flash memory before accessing user data as shown below.
Adding DRAM cache for the FTL data to the storage controller chip would increase the chip size and power consumption, which is unsuitable for resource-limited IoT devices. Instead, we propose to cache the FTL data on the host DRAM and to have the SMMU perform this additional address translation. The following figure shows the proposed storage architecture and a micrograph of the prototype chip that can access the host FTL. As the result of eliminating the additional FTL flash memory access, the access latency is reduced from 270 usec to 133 usec.
Network caching is needed for mapping remote IoT devices on a single address space. However, it is unlikely that wireless network infrastructures alone will be able to satisfy growing mobile data traffic. We are developing a system for ad hoc device-to-device data relay, where each device caches data, so that other nearby devices can access it via proximity-based wireless communication (e.g., Wi-Fi) without going through preexisting networks.
 |
Distributed devices connected via a preexisting wireless network. |
 |
Devices connected directly with each other nearby, where, as opposed to mesh networks, data is transferred in a store-and-forward way so that each device acts as network cache. |
As a first step, we consider presumably the simplest scenario of one IoT device delivering data to others in the same area. The challenge here is to efficiently transfer data by avoiding radio interference in the absence of central control, which we address by using multicast transmission augmented with a packet repair mechanism, along with adaptive selection of relay nodes according to signal levels of nearby devices.
The following figure shows a snapshot of network simulation where green/blue dots indicate devices that have received the data, while red dots indicate those that have not.
The simulation indicates that our method delivers 128kB data to 7000 devices in 50 sec, which is seven times faster than naive unicast flooding (1000 devices in 50 sec).
The prototype device shown below is equipped with a FlashAir Wi-Fi SD card with modified firmware as a wireless network adapter, to have more control over the multicast bitrate and transmission power than typical off-the-shelf adapters in order to optimize performance.
