Media Processing with Field-Programmable Gate Arrays on a
Microprocessor's Local Bus
V. Michael Bove, Jr., Mark Lee, Yuan-Min Liu, Christopher
McEniry, Thomas Nwodoh, John Watlington
The Chidi system is a PCI-bus media processor card which performs its
processing tasks on a large field-programmable gate array (Altera
10K100) in conjunction with a general purpose CPU (PowerPC 604e).
Special address-generation and buffering logic (also implemented on
FPGAs) allows the reconfigurable processor to share a local bus with
the CPU, turning burst accesses to memory into continuous streams and
converting between the memory's 64-bit words and the media data types.
In this paper we present the design requirements for the Chidi system,
describe the hardware architecture, and discuss the software model for
its use in media processing.
Keywords: video compression, field-programmable gate array, data-flow
computing, digital signal processing
MIT Media Laboratory
Proc. SPIE Media Processors, 3655, 1999.